Better Circuits for Binary Polynomial Multiplication

Magnus Gaudal Find; René Peralta

doi:10.1109/TC.2018.2874662

Better Circuits for Binary Polynomial Multiplication

IEEE Trans Comput. 2019:68:10.1109/TC.2018.2874662. doi: 10.1109/TC.2018.2874662.

Authors

Magnus Gaudal Find¹, René Peralta²

Affiliations

¹ National Institute of Standards and Technology, Gaithersburg, MD 20899.
² Computer Security Division, National Institute of Standards and Technology, Gaithersburg, MD 20899.

Abstract

We develop a new and simple way to describe Karatsuba-like algorithms for multiplication of polynomials over $F_{2}$ . We restrict the search of small circuits to a class of circuits we call symmetric bilinear. These are circuits in which AND gates only compute functions of the form $\sum_{i \in S} a_{i} \cdot \sum_{i \in S} b_{i}$ (S ⊆ {0,…, n - 1}). These techniques yield improved recurrences for M(kn), the number of gates used in a circuit that multiplies two kn-term polynomials, for k = 4, 5, 6, and 7. We built and verified the circuits for n-term binary polynomial multiplication for values of n of practical interest. Circuits for n up to 100 are posted at http://cs-www.cs.yale.edu/homes/peralta/CircuitStuff/BinPolMult.tar.gz.

Keywords: Binary polynomial multiplication; circuits; symmetric bilinear circuits.

Grants and funding

9999-NIST/Intramural NIST DOC/United States